1. Field of the Invention
The present invention generally relates to digital-to-analog converters and more particularly to a digital-to-analog converters and associated methods.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “logical signal,” “clock,” “transistor,” “MOS (metal-oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “gate,” “drain,” “source,” “threshold voltage,” “circuit node,” “power supply node,” “ground node,” and “switch.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus need not be explained in detail here.
Throughout this disclosure, a logical signal refers to a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal.
A logical signal is said to be asserted when it is high. A logical signal is said to be de-asserted when it is low.
As is known, a digital-to-analog converter (DAC) receives a digital signal and outputs an analog signal, wherein the value of the analog signal represents a value of the digital signal. A capacitive DAC comprises a capacitor, a voltage of which represents an analog signal determined by a value of a digital signal. FIG. 1 shows a schematic diagram of a prior art capacitive DAC 100, which comprises: a capacitor 120 and a switch network 110. A first end 121 of the capacitor 120 couples to an output node 101, and a second end 122 of the capacitor 120 couples to an input node 113. The switch network 110 comprises a PMOS (p-channel metal oxide semiconductor) transistor 111 and a NMOS (n-channel metal oxide semiconductor) transistor 112, and is controlled by a digital signal DD, which is a logical signal. When the digital signal DD is asserted (de-asserted), the NMOS (PMOS) transistor 112 (111) is turned on while the PMOS (NMOS) transistor 111 (112) is turned off, and the input node 113 is coupled to a low (high) reference voltage VRL (VRH) via the NMOS (PMOS) transistor 112 (111). The high reference voltage VRH is higher than the low reference voltage VRL, and therefore a voltage at the output node 101 is higher when the digital signal DD is de-asserted than when the digital signal DD is asserted. The voltage at the output node 101 thus represents a value of the digital signal DD.
Implementation details of FIG. 1 (for instance, the source, the gate, and the drain of the PMOS transistor 111 couple to the high reference voltage VRH, the digital signal DD, and the input node 113, respectively) will be understood to those of ordinary skill in the art and thus are not explained here. Upon a change of value of the digital signal DD, a switching activity takes place within the switch network 110. For a high-speed application, the voltage at the output node 101 must change quickly in response to the change of value of the digital signal DD. To enable the voltage at the output node 101 to change quickly in response to a high-to-low (low-to-high) change of the value of the digital signal DD, a large sourcing (sinking) current IH (IL) must be provided from (to) the high (low) reference voltage VRH (VRL) via the PMOS (NMOS) transistor 111 (112). Although not explicitly shown in FIG. 1, the high reference voltage VRH and the low reference voltage VRL come from a respective reference voltage generation circuit. To allow a large sourcing or sinking current, the respective reference voltage generation circuit must have a high driving capability, as known by those of ordinary skill in the art.
What is desired is a high-speed DAC circuit that relaxes a requirement of a driving capability of a reference voltage generation circuit.